
ISD5008
Publication Release Date: Oct 31 2008
- 22 -
Revision 1.2
6.4.4
SPI Port
The following diagram describes the SPI port and the control bits associated with it.
Byte 1
Byte 2
Byte 3
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C0 C1 C2 C3 C4 C5 C6 C7
MOSI
Reserved
Load CFG0 (LC0)
Load CFG1 (LC1)
Message Cueing
Ignore Address Bit
PowerUp
Play/Record
Run
6.4.5
SPI Control Register
The SPI control register provides control of individual device functions such as Play, Record, Message
Cueing, Power-Up and Power-Down, Start and Stop operations, Ignore Address Pointers and Load
Configuration Registers.
TABLE 7: SPI CONTROL REGISTER
Control
Register
Bit
Device Function
Control
Register
Bit
Device Function
RUN
=
1
0
Enable or Disable an operation
Start
Stop
PU
=
1
0
Master power control
Power-Up
Power-Down
P/
R
=
1
0
Selects Play or Record operation
Play
Record
IAB
=
1
0
Ignore address control bit
Ignore input address register (A15-
A0)
Use the input address register
contents for an operation (A15-A0)
MC
=
1
0
Enable or Disable Message
Cueing
Enable Message Cueing
Disable Message Cueing
A15-A0
Output of the row pointer register
D15-D0
Input control and address register
LC0
=
1
0
Load Configuration Reg 0
No Load
LC1
=
1
0
Load Configuration Reg 1
No Load